Intel Parallel Studio XE 2018 is the latest version of Intel’s comprehensive tool suite for modernizing software on Intel® architectures. In honor of its release, we’ve included several articles on Intel Parallel Studio XE components in this issue. Modernize Your Code for Performance, Portability, and Scalability gives a high-level overview of the many new features and capabilities in this tool suite. (You can also learn more in my blog on the release of Intel Parallel Studio XE 2018.) Dealing with Outliers shows how to detect fraud in a real-world dataset of credit card transactions, using the Intel® Data Analytics Acceleration Library to achieve high accuracy at very high performance.
Intel Parallel Studio XE has always supported OpenMP*. The latest release supports OpenMP 4.5 and many features of the 5.0 draft specification. We close out our celebration of OpenMP’s 20th birthday with a final guest editorial, this one from Barbara Chapman, Professor at Stony Brook University and Director of Computer Science and Mathematics at Brookhaven National Laboratory. In Welcome to the Adult World, OpenMP, Barbara discusses the early success of OpenMP and why it’s likely to remain a vital parallel programming model for years to come.
The Intel® HPC Developer Conference (November 11-12 in Denver, CO) and SC17 (November 12-17, also in Denver) are just around the corner, so this issue contains three articles devoted to HPC. We explore Intel® Cluster Checker in Is Your Cluster Healthy? This component of Intel Parallel Studio encapsulates many best-known methods and system diagnostics to keep clusters operating efficiently.
Several BIOS options can affect application performance, but it’s difficult to change these options on demand in a production cluster environment. Learn about a technique to enable on-demand BIOS configuration changes in Optimizing HPC Clusters. And Effectively Using Your Whole Cluster presents a case study of HPC application tuning using several of the tools in Intel Parallel Studio XE.
The Heterogeneous Parallel Computing Future
The future is heterogeneous. (Actually, CPUs and GPUs have existed within the same system—and even on the same processor die—for many years now, so heterogeneous computing is already here.) Just as multicore processors have made parallelism ubiquitous, it won’t be long before CPU, GPU, FPGA, ASIC, etc. coexisting within the same system makes heterogeneous parallelism ubiquitous, too. I used to worry about the heterogeneous future, but new parallel programming models will make it easier to map computations to the most efficient processor architecture. The Intel® Threading Building Blocks Flow Graph API is one such approach.
This API has already been covered in The Parallel Universe (see “Heterogeneous Programming with Intel® Threading Building Blocks” in our special issue), so I won’t discuss it here, but this issue’s feature article, Driving Performance with Intel® Advisor’s Flow Graph Analyzer, gives an in-depth look at the Flow Graph Analyzer technology preview feature in Intel Parallel Studio XE. We use an autonomous driving application to illustrate the flow graph computation and analysis.
The Parallel Universe welcomes back its founding editor, James Reinders, to continue the theme of heterogeneity. In Enabling FPGAs for Software Developers, James and Bernhard Friebe discuss FPGA programming from a software, rather than a hardware, development perspective. Look for a follow-up article on FPGA programming in our next issue.
Finally, we close out this issue with a detailed look at what’s new in the AVX-512 instruction set architecture. Tuning for Success with the Latest SIMD* Extensions and Intel® Advanced Vector Extensions 512 discusses best practices in performance tuning with the new SIMD language extensions for AVX-512 and the latest support in the Intel compilers for the Intel® Xeon® Scalable processors.
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