This tutorial shows you how to create the hardware equivalent of “Hello World”: a blinking LED. This is a simple exercise to get you started using the Intel® Quartus® software for FPGA development.
You’ll learn to compile Verilog code, make pin assignments, create timing constraints, and then program the FPGA to blink one of the eight green user LEDs on the board. You'll use a 50 MHz clock input (from the on-board oscillator) to drive a counter, and assign an LED to one of the counter output bits.
Terasic DE10-Nano kit
The Terasic DE10-Nano development board, based on an Intel® Cyclone V SoC FPGA, provides a reconfigurable hardware design platform for makers, IoT developers and educators. You can buy the kit here.
Intel® Quartus® Prime Software Suite Lite Edition
The FPGA design software used here is ideal for beginners as it’s free to download and no license file is required. You can download the software here.
Once you’ve downloaded and installed the Intel® Quartus® software, you're ready to get started creating a project!
Why is the Quartus download so big?
Step 1: Create an Intel® Quartus® Software Project
Step 1.a: Open Intel® Quartus® Prime Software Suite Lite Edition.
Step 1.b: Open a New Project Wizard
Step 1.c: Select Next
Step 1.d: Directory, Name, Top-Level Entity
Choose a directory to put your project under. Here, we name our project “Blink” and place it under the intelFPGA_lite folder but you can place it wherever you want. Select Next.
When prompted to create the directory, choose Yes.
Step 1.e: Project Type
Select Empty Project, and then click Next.
Step 1.f: Add Files
You won’t be adding any files here. Click Next.
Step 1.g: Family, Device, and Board Settings (Note: You may need to expand window to view more device names)
Select the following:
Family: Cyclone V
Device: Cyclone V SE Base
Device name: 5CSEBA6U23I7NDK
Step 1.h: EDA Tool Settings
We will be using the default EDA tools and settings so there are no changes to be made. Click Next.
Step 1.i: Summary
The following screen displays.
Step 2: Create an HDL File
Hardware Description Language (HDL)
We use Verilog as the HDL. If you are familiar with the C programming language but new to programming in an HDL, Verilog is like C in that you place a semicolon ‘;’ at the end of each statement.
Step 2.a: Navigate to the File tab (main window), and then select New.
Select Verilog HDL File, and then click OK.
Step 2.b: Choose File > Save As. Choose “blink” for the file name. This is your top-level file name and it must match the name of the project name (blink). Click Save.
Step 3: Create a Verilog Module
Step 3.a: Copy and paste this Verilog code into the blink.v window, and then save the file.
// create module
module blink (
input wire clk, // 50MHz input clock
output wire LED // LED ouput
// create a binary counter
reg [31:0] cnt; // 32-bit counter
cnt <= 32'h00000000; // start at zero
always @(posedge clk) begin
cnt <= cnt + 1; // count up
//assign LED to 25th bit of the counter to blink the LED at a few Hz
assign LED = cnt;
Step 3.b: Analysis & Synthesis
Right click on Analysis and Synthesis”, and then click Start to perform a syntax check and synthesis of the Verilog code.
What happens during analysis and synthesis?
If the process completes successfully, a green check mark displays next to Analysis & Synthesis. If you get an error, check your syntax and make sure it matches exactly the code block provided above. Be sure you used the “View Source” button when you copied the text in step 3.a above.
Step 4: Choose Pin Assignments
Step 4.a: In the top navigation bar, select Assignments > Pin Planner.
Notice that the input (clk) and output (LED) are listed under Node Name. This is because you ran the Analysis & Synthesis.
Step 4.b: One at a time, click to highlight the Location column for each pin, then type the pin location for the LED and clk signals as shown below. The rest of the columns will auto populate with data (some with default values that we’ll modify in the next step).
You also need to change the I/O standard, Current Strength and Slew Rate columns from their default settings to the values shown below:
Step 4.c: To change the I/O standard, double click each cell and a pull-down menu will appear. Click the down arrow icon and scroll to the desired value. Change the I/O standard from the default 2.5V to 3.3-V LVTTL.
Step 4.d: The Current Strength will by default read 16ma(default) and we need to select 16ma. If we don’t specifically set them, then we get warning messages in our compilation. Set Current Strength to 16mafor both input (clk) and output (LED).
Step 4.e: Next change Slew Rate for the LED output from 1(default) to 1(fast). You don’t need to set a Slew Rate for the clk. Leave that blank.
Step 4.f: Close the Pin Planner.
Step 5: Create an SDC File
Before you compile the Verilog code, you need to provide timing constraints for the design. You'll create an SDC (Synopsis Design Constraints) file that contains commands to let the Intel® Quartus® software know how to close timing on the design. Without it, you will get warning messages in the compile flow because the Intel® Quartus® software has no idea how to close timing on the design.
To create a blink.sdc and add it to the blink file directory, do the following.
Copy and paste the following content into a text editor (e.g. notepad):
# inform quartus that the clk port brings a 50MHz clock into our design so
# that timing closure on our design can be analyzed
create_clock -name clk -period "50MHz" [get_ports clk]
# inform quartus that the LED output port has no critical timing requirements
# its a single output port driving an LED, there are no timing relationships
# that are critical for this
set_false_path -from * -to [get_ports LED]
Now save the file as a .sdc file. Place in the blink file directory – same directory where our verilog file (.v file extension) lives.
What is an SDC file, and why do I need one?
Step 6: Compile the Verilog Code
Right click on Compile Design, and then click Start. The tools will then synthesize, place and route, assemble and perform timing analysis on the design Because there are only have a handful of code lines, the compilation should only take a couple of minutes to complete.
What happens during the fitter (place & route)?
What happens during the assembler?
What is timing analysis?
After compilation is complete you will see a summary report like the one below.
After you compile the Verilog code, you can program the FPGA.
Step 7: Program the FPGA
The final step is to program the FPGA. Before we do that, be sure to remove the SD Card from the board.
Why should I remove the SD Card?
Step 7.a: Connect the board to your computer via the USB blaster port. Use the USB cable (mini-b connector) that came with the Terasic DE10-Nano kit. Insert the mini-b connector into the USB Blaster port (J13) on the Terasic DE10-Nano board and the Type-A end into a standard USB port on your host computer.
Step 7.b: Connect the board to power and verify there is a blue LED lit near the J13 USB Blaster II port.
Step 7.c: Right click to open Program Device.
Step 7.d: Hardware Setup
Select Hardware Setup.
Under the drop down for Currently selected hardware, choose DE-SoC, then click Close.
Step 7.e: Click Auto Detect to identify the JTAG chain on the board.
Select the device 5CSEBA6. This is the FPGA device.
Step 7.f: Add the .sof file.
Right click on the File column for the 5CSEBA6 device and select Change File.
Why are there two devices found in the JTAG chain?
Step 7.g: Navigate to the output_files folder, select blink.sof, and then click Open.
Here, blink.sof is your programming file. SRAM Object Files (.sof files) are binary files containing data for configuring SRAM-based devices—our FPGA is based on SRAM—using the Intel® Quartus® software Program Device (also called Programmer). The programmer looks into the SOF file and gets the programming bit stream for the device.
Step 7.h: Check the Program/Configure column, and then click Start.
Step 8: Observe the blinking LED
If your progress bar is 100% (Successful), watch LED [7:0] to go through a blinking sequence.
Experiment on Your Own
Change the Blink Rate
Now that you’ve got one successful blinking LED under your belt, you can modify the blink rate of the LED by using a different “bit” of the counter. 1 Hertz is 1/second (cycles per second) and blinking at 1 Hz means the LED blinks once per second. For 2 Hz, the LED blinks twice per second. And 0.25 Hz would blink the LED once every 4 seconds (slow blink). For a slower blink, use a higher bit of the counter and for faster, use a smaller bit (e.g., cnt). Test out different counter bits and see what you get.
Clock and Counter Math
cnt[n] where n = the counter bit
2^n; we've chosen n = 24 in our Verilog code sample
2^24 = 16,777,216
Our clock is 50 MHZ or 50,000,000
Clock / 2^n = blinks per second
50,000,000 / 16,777,216 = 2.9802
That’s about 3 blinks per second.
To make this change, you will need to:
1. Modify the Verilog file (blink.v) and select a different counter bit in the assignment statement.
2. Recompile the design
3. Reprogram the FPGA
Add More LEDs
Try connecting one or more of the remaining 7 LEDs to other counter bits, with each blinking at a different rate. For example, you could add a new LED connected to counter bit 23 which would blink twice as fast as bit 24. Or you could add all the remaining 7 LEDs and connect each to a unique counter bit.
To make this change, you will need to:
1. Modify the Verilog code (step 3a):
1. Add the new LEDs to the module definition
2. List the new LEDs as being outputs
3. Assign each of the new LEDs to a unique counter bit (cnt[n])
I’m new to hardware design. Where can I get a Verilog file that contains these changes?
2. Run Analysis and Synthesis (step 3b)
3. Assign the LEDs outputs to pins using the Pin Planner (steps 4b - 4e).
Be sure to set the proper I/O standard, drive strength, and slew rate. The I/O pin connected to the LEDs are as follows:
3. Recompile the design (step 6a)
4. Reprogram the device (step 7h)
For more such intel IoT resources and tools from Intel, please visit the Intel® Developer Zone